Computer Science Colloquium
Im Rahmen des Informatik-Kolloquiums, das von den Instituten des Fachbereichs Informatik, der Österreichischen Gesellschaft für Informatik (ÖGI), der Arbeitsgemeinschaft für Datenverarbeitung (ADV) sowie der Österreichischen Computergesellschaft (OCG) abgehalten wird, sprichtClifford Wolf
über das Thema:Formal Verification of Verilog HDL with Yosys-SMTBMC and SymbiYosys
Zeit: Mon 6.3.2017, 13:00, 120 MinutenOrt: Science Park 2, S2 Z74
Zusammenfassung
Yosys is a free and open source Verilog synthesis tool and more. In this presentation we discuss Yosys-SMTBMC, a Yosys-based formal verification flow that can use any SMT-LIB2 solver as back-end engine, and SymbiYosys, a uniform front-end for various Yosys-based formal flows, including Yosys-SMTBMC and flows utilising AIGER-based engines.Vortragender
Clifford Wolf develops open source software, has been teaching at Metalab and collaborates and publishes with the Institute of Computer Technology, of the Vienna University of Technology. He is particularly interested in developing high quality open source solutions for Electronic Design Automation (EDA), which are software tools for industrial hardware design.Einladender: Prof. Dr. Armin Biere, Institute of Formal Models and Verification
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